1. Field of the Invention
The present invention relates to serial data communications and more particularly to high-speed serial data communcations with digital computing devices lacking the capability of direct memory access (DMA).
2. State of the Art
Personal computers with modems now access a wide variety of networks. Although modem communications is generally adequate for exchanging text files, the transmission of digital voice, fax and video data, especially simultaneous, requires a data rate that exceeds the capabilites of most modems. The Integrated Services Digital Network (ISDN) is designed to provide what appears to the user to be one unified network satisfying all user needs. Demonstrations networks are currently being installed in several countries. In ISDN networks, a digital adapter serves as the communications equipment. Since the data is digital throughout the network, the function of a modem becomes unnecessary.
Newer computers are typically equipped with high-speed serial interfaces that use direct memory access (DMA). Older machines and less-expensive machines, however, are generally equipped with relatively slow serial interfaces that lack DMA capability. These machines typically have interface circuitry that must be totally serviced by the central processing unit (CPU).
In a typical computer equipment interface, shown in simplified form in FIG. 1, a Universal Synchronous/Asynchronous Receiver Transmitter (USART) handles most of the format conversions needed. USARTs allow users to specify operating characteristics of supported equipment by loading a predefined code word or bit pattern. Level converters convert voltages from those used by the physical layer (serial cable) to those for computer equipment. Control signals pass across the interface. The USART uses program addressable Receiver Status and Transmitter Status Registers to store precise status, including, for example (in accordance with the RS-232C standard) the status of Ring, Request to Send, Clear to Send, Data Set Ready, Data Terminal Ready, and Carrier Detect lines, bits to enable interrupts and cause them if they are enabled, and so forth. These bits include one for Received Data Available (RDA) in the Receiver Status Register and one for Transmitter Buffer Empty (TBMT) in the Transmitter Status Register, both of which are set, when appropriate, by the USART.
When a register is read, the Address Selection Logic gates contents of the appropriate register (Receiver Buffer, Receiver Status Register or Transmitter Status Register) onto the CPU bus data lines. Conversely, when a register is written, data on the CPU bus come into the Bus Receivers and are presented to the appropriate register via the Parallel Data lines. The Address Selection Logic then strobes the data into the register.
During receiving, all bits comprising a character are assembled in the USART. It then sets the RDA bit in the Receiver Status Register, causing an interrupt to be generated as soon as interrupts are enabled. The computer program responds to the interrupt and reads the Receiver Buffer. It next uses a circuit, Reset Data Available, to assure the USART that it is safe to replace data in its Receive Buffer with new data. If this is not finished before the USART needs to shift a character into the buffer (in order to have space to assemble a new character), a bit indicating Overrun Error is set and passed to the CPU to deal with as it wishes.
During transmission, the USART sets the TBMT bit when the Transmit Buffer is empty. This bit is passed to a Transmitter Status Register in the CPU and causes an interrupt. The CPU checks to see if it has anything to send on the line. If it does, it loads it into the USART""s Transmit Buffer and clears the TBMT bit. The USART shifts the character from the Transmit Buffer into another register, resetting the TBMT bit, and shifts the character out a bit at a time.
Referring to FIG. 2, showing a block diagram of a typical USART, the USART can operate as either a synchronous or an asynchronous receiver/transmitter, depending on bits in the Mode Register. Bits in this register also determine the number of bits per character, whether even parity, odd parity, or no parity is used, and details of treatment of certain characters. In addition, for asynchronous mode, the register determines the speed of the transmit and receive clocks with respect to the bit rate.
The Status Register contains the Received Data Available (RDA) and Transmitter Buffer Empty (TBMT) bits discussed above, plus bits indicating Parity Error, Framing Error, and Overrun Error and bits for modem control. Since the USART is programmable, simple commands cause it to examine status bits and execute transmit and receive functions.
During synchronous data reception, the USART uses incoming clock signals to determine when to sample voltage on the Received Data line; each sample is classified as a xe2x80x9c0xe2x80x9d or xe2x80x9c1xe2x80x9d and shifted into the Receive Register. When this register is full, the bits are shifted in parallel into the Receive Buffer and the RDA bit is set, causing an interrupt to the CPU. The USART also searches for characters that indicate frames are starting, using information in its Mode Register. Error bits in the Status Register are set when errors are detected.
During synchronous data transmission, characters obtained from the CPU, after interrupts initiated by the TBMT bit, are shifted in parallel from the Transmit Buffer to the Transmit Register and out onto the line a bit at a time. The USART automatically inserts control characters to start frames. As soon as a character has been shifted into the Transmit Register, the TBMT bit is set and the process restarts. Data reception and transmission can go on simultaneously in a full duplex manner.
The primary difference between synchronous and asynchronous operation is in clocking; no external clocking is available for asynchronous operation. A clock running at approximately some multiple of the bit rate (16 to 64 times) is used. Voltage on the Received Data line is examined each clock time until a transition from xe2x80x9c1xe2x80x9d to xe2x80x9c0xe2x80x9d is seen. This is a transition from an idle line condition to the voltage for a START bit. If the clock is running at 16 times the bit rate, further samples are taken 8, 24, 40, and so forth, clock times later. The first sample should be approximately at the middle of the START bit, the second near the middle of the first data bit, and so forth. Given a reasonably accurate clock, sampling times are accurate enough to sample all bits in a character. The sampled bits are shifted into the Receiver Register, with the rest of the operation essentially the same as for the synchronous case.
Transmission of asynchronous data using the USART is done in the same manner as transmission of synchronous data, except for using the internal clock instead of an externally derived clock, and shifting a bit out once every 16 (to 64) clock cycles instead of every clock cycle.
Somewhat more sophisticated than a simple USART is a Serial Communications Controller (SCC, for example device number Am8530H sold by Advanced Micro Devices). The SCC is able to pull out data portions of received frames, discarding overhead information, or inserting overhead information in transmitted frames. Error detection with polynomial codes commonly used with data link controls are also implemented.
The interface of FIG. 1 is limited in its performance. The interface can use excessive CPU cycles responding to interrupts, since it interrupts the CPU for every character received or transmitted. Interrupt service routines for typical communications interfaces take 25 to 200 us, with getting into the service routine and out of it again sometimes taking nearly as much time as the service routine itself. High-speed serial interfaces, on the other hand, use DMA to read or write blocks of data without interrupting the CPU, except to initiate or conclude block transfers or deal with exceptional conditions.
In order to allow non-DMA capable machines (including older machines and current less-expensive machines) to function in an ISDN or similar environment, a more powerful serial interface mechanism is required.
The present invention, generally speaking, provides for the exchange of high-speed data streams between two digital computing devices one or both of which lacks DMA. In a preferred embodiment, data transfers are performed by the devices using High-Level Datalink Control (HDLC) frames. An initiating device indicates that it wishes to exchange data with the other device by sending an HDLC frame. The initial HDLC frame is sufficiently short that at least an essential portion of the frame can be stored in a receive buffer of the interface circuitry. Although the receiving device may not receive the entire HDLC frame correctly because of the possibility of an overrun condition, enough information is preserved in the interface circuitry to complete the transaction. The responding device then proceeds to read or write data at high speed using a series of exchanges with the initiating device.